Module Verilog_parsing.LabelsSource
Sourcetype wirespec = | WS_NORMAL| WS_UNRESOLVED
Sourcetype gate = | BUFIF0| BUFIF1| CMOS| NMOS| PMOS| NOTIF0| NOTIF1| PULLDOWN| PULLUP| RCMOS| RNMOS| RPMOS| RTRAN| RTRANIF0| RTRANIF1| TRAN| TRANIF0| TRANIF1