Module Hardcaml_xilinxSource

Sourcemodule Address_collision : sig ... end

Handling of address collisions between ports in native Xilinx RAM technologies.

Sourcemodule Byte_write_width : sig ... end
Sourcemodule Cascade_height : sig ... end

Height of BRAM cascades chains. This can be explicitly specified to help vivado meet timing when it is unnecessarily cascading BRAMs.

Sourcemodule Clocking_mode : sig ... end
Sourcemodule Collision_mode : sig ... end
Sourcemodule Dual_port_ram : sig ... end

Single clock Dual Port Memory

Sourcemodule Fifo_async : sig ... end
Sourcemodule Fifo_memory_type : sig ... end
Sourcemodule Fifo_sync : sig ... end
Sourcemodule Xilinx_memory_builder : sig ... end

A general-purpose means of representing memories. The Config.t type allows the user to configure the underlying memory implementations. Eg: Using URAM for bits 0-72, and BRAMs for bits 73-80. This module allows construction of memories in 1D or 2D Modes. See further documentation below.

Sourcemodule Ram_arch : sig ... end

Xilinx RAM primitive types.

Sourcemodule Ram_port : sig ... end
Sourcemodule Ram_port_with_clear : sig ... end

State machine for clearing a RAM via one of it's ports.

Sourcemodule Ram_with_resizing : sig ... end

Optionally generate XPM URAM instances with an additional wrapper layer to avoid issues where Vivado will change the read before write and write before read behavior of the RAM causing simulation mismatches. Only seems to occur when READ_LATENCY is greater than 1.

Sourcemodule Simple_dual_port_ram : sig ... end

Simple Dual Port Memory. 1 port is for writing, the other for reading.

Sourcemodule Synthesis : sig ... end
Sourcemodule True_dual_port_ram : sig ... end