Module Ast.Addressing_mode

module Offset : sig ... end
type single = [
  1. | `Base_reg
  2. | `Offset_twelve_unsigned_scaled
  3. | `Offset_nine_signed_unscaled
  4. | `Offset_sym
  5. | `Literal
  6. | `Pre
  7. | `Post
]
type _ t = private
  1. | Reg : [ `GP of [< `X | `SP ] ] Reg.t -> [> `Base_reg ] t
  2. | Offset_twelve_unsigned_scaled : [ `GP of [< `X | `SP ] ] Reg.t * [ `Twelve_unsigned_scaled ] Addressing_offset.t -> [> `Offset_twelve_unsigned_scaled ] t
  3. | Offset_nine_signed_unscaled : [ `GP of [< `X | `SP ] ] Reg.t * [ `Nine_signed_unscaled ] Addressing_offset.t -> [> `Offset_nine_signed_unscaled ] t
  4. | Offset_sym : [ `GP of [< `X | `SP ] ] Reg.t * [ `Twelve ] Symbol.t -> [> `Offset_sym ] t
    (*

    PC-relative literal load addressing. Architecturally, LDR Xt, <label> encodes a 19-bit signed offset from PC to the label (±1MB range). No base register is involved.

    Note: The emitter currently uses ADRP+LDR sequences instead of true literal loads, which allows arbitrary distances. This addressing mode is available for future use if needed.

    *)
  5. | Literal : [ `Nineteen ] Symbol.t -> [> `Literal ] t
  6. | Pre : [ `GP of [< `X | `SP ] ] Reg.t * [ `Nine_signed_unscaled ] Offset.t -> [> `Pre ] t
  7. | Post : [ `GP of [< `X | `SP ] ] Reg.t * [ `Nine_signed_unscaled ] Offset.t -> [> `Post ] t
  8. | Offset_pair : [ `GP of [< `X | `SP ] ] Reg.t * [ `Seven_signed ] Offset.t -> [> `Offset_pair ] t
  9. | Pre_pair : [ `GP of [< `X | `SP ] ] Reg.t * [ `Seven_signed ] Offset.t -> [> `Pre_pair ] t
  10. | Post_pair : [ `GP of [< `X | `SP ] ] Reg.t * [ `Seven_signed ] Offset.t -> [> `Post_pair ] t