Module Hardcaml_kernel.ParameterSource

A Parameter.t is the name and value of a configurable attribute of an instantiated RTL design.

In Verilog they are called parameterss and in VHDL they are called generics.

Sourcemodule Value : sig ... end
Sourcetype t = {
  1. name : Parameter_name.t;
  2. value : Value.t;
}
include Bin_prot.Binable.S with type t := t
include Bin_prot.Binable.S_only_functions with type t := t
include sig ... end
Sourceval bin_size_t : t Bin_prot.Size.sizer
Sourceval bin_write_t : t Bin_prot.Write.writer
Sourceval bin_read_t : t Bin_prot.Read.reader
Sourceval __bin_read_t__ : t Bin_prot.Read.vtag_reader

This function only needs implementation if t exposed to be a polymorphic variant. Despite what the type reads, this does *not* produce a function after reading; instead it takes the constructor tag (int) before reading and reads the rest of the variant t afterwards.

Sourceval bin_shape_t : Bin_prot.Shape.t
Sourceval sexp_of_t : t -> Sexplib0.Sexp.t
include Base.Equal.S__local with type t := t
Sourceval create : name:string -> value:Value.t -> t
Sourceval find_name : t list -> Parameter_name.t -> Value.t Core.Option.t
Sourceval find_name_exn : t list -> Parameter_name.t -> Value.t
Sourceval is_subset : t list -> t list -> bool

is_subset ts1 ts2 returns true iff every t in ts1 is in ts2.

Sourceval sort_by_name : t list -> t list