Module Hardcaml_kernel.ClockingSource

Sourcemodule type S = sig ... end
Sourcemodule Make () : S
include S with type 'a t = 'a Hardcaml_kernel__.Clocking_intf.Untyped.t
Sourcetype 'a t : immutable_data = {
  1. clock : 'a;
  2. clear : 'a;
}
include Ppx_compare_lib.Comparable.S1 with type 'a t := 'a t
include Ppx_compare_lib.Comparable.S1__local with type 'a t := 'a t
include Ppx_compare_lib.Equal.S1 with type 'a t := 'a t
include Ppx_compare_lib.Equal.S1__local with type 'a t := 'a t
include Interface.S with type 'a t := 'a t
include Hardcaml_interface_types.Pre with type 'a t := 'a t
include Hardcaml_interface_types.Pre_partial with type 'a t := 'a t
include Ppx_compare_lib.Equal.S1 with type 'a t := 'a t
include Ppx_compare_lib.Equal.S1__local with type 'a t := 'a t
include Ppx_compare_lib.Comparable.S1 with type 'a t := 'a t
Sourceval compare : ('a -> 'a -> int) -> 'a t -> 'a t -> int
include Ppx_compare_lib.Comparable.S1__local with type 'a t := 'a t
Sourceval sexp_of_t : ('a -> Sexplib0.Sexp.t) -> 'a t -> Sexplib0.Sexp.t
Sourceval iter : 'a t -> f:('a -> unit) @ local -> unit
Sourceval iter2 : 'a t -> 'b t -> f:('a -> ('b -> unit) @ local) @ local -> unit
Sourceval map : 'a t -> f:('a -> 'b) @ local -> 'b t
Sourceval map2 : 'a t -> 'b t -> f:('a -> ('b -> 'c) @ local) @ local -> 'c t
Sourceval to_list : 'a t -> 'a list
Sourceval port_names_and_widths : (string * int) t
include Base.Equal.S1__local with type 'a t := 'a t
Sourceval port_names : string t

RTL names specified in the interface definition - commonly also the OCaml field name.

Sourceval port_widths : int t

Bit widths specified in the interface definition.

Sourceval const : 'a -> 'a t

const x sets each port to x

Sourcetype tag
Sourceval equal_tag : tag -> tag -> bool
Sourceval equal_tag__local : tag @ local -> tag @ local -> bool
Sourceval tags : tag t
Sourceval to_alist : 'a t -> (tag * 'a) list

Create association list indexed by tag.

Sourceval of_alist : (tag * 'a) list -> 'a t

Create interface from association list indexed by tag.

Sourceval sum_of_port_widths : int

Sum of all port widths specified in the interface definition.

Sourcemodule Unsafe_assoc_by_port_name : sig ... end
Sourceval zip : 'a t -> 'b t -> ('a * 'b) t
Sourceval zip3 : 'a t -> 'b t -> 'c t -> ('a * 'b * 'c) t
Sourceval zip4 : 'a t -> 'b t -> 'c t -> 'd t -> ('a * 'b * 'c * 'd) t
Sourceval zip5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> ('a * 'b * 'c * 'd * 'e) t
Sourceval map3 : 'a t -> 'b t -> 'c t -> f:('a -> ('b -> ('c -> 'd) @ local) @ local) @ local -> 'd t
Sourceval map4 : 'a t -> 'b t -> 'c t -> 'd t -> f:('a -> ('b -> ('c -> ('d -> 'e) @ local) @ local) @ local) @ local -> 'e t
Sourceval map5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> f: ('a -> ('b -> ('c -> ('d -> ('e -> 'f) @ local) @ local) @ local) @ local) @ local -> 'f t
Sourceval iter3 : 'a t -> 'b t -> 'c t -> f:('a -> ('b -> ('c -> unit) @ local) @ local) @ local -> unit
Sourceval iter4 : 'a t -> 'b t -> 'c t -> 'd t -> f:('a -> ('b -> ('c -> ('d -> unit) @ local) @ local) @ local) @ local -> unit
Sourceval iter5 : 'a t -> 'b t -> 'c t -> 'd t -> 'e t -> f: ('a -> ('b -> ('c -> ('d -> ('e -> unit) @ local) @ local) @ local) @ local) @ local -> unit
Sourceval fold : 'a t -> init:'acc -> f:('acc -> ('a -> 'acc) @ local) @ local -> 'acc
Sourceval fold2 : 'a t -> 'b t -> init:'acc -> f:('acc -> ('a -> ('b -> 'acc) @ local) @ local) @ local -> 'acc
Sourceval scan : 'a t -> init:'acc -> f:('acc -> ('a -> 'acc * 'b) @ local) @ local -> 'b t
Sourceval scan2 : 'a t -> 'b t -> init:'acc -> f:('acc -> ('a -> ('b -> 'acc * 'c) @ local) @ local) @ local -> 'c t
Sourceval offsets : ?rev:bool -> unit -> int t

Offset of each field within the interface. The first field is placed at the least significant bit, unless the rev argument is true.

Sourceval of_interface_list : 'a t list -> 'a list t

Take a list of interfaces and produce a single interface where each field is a list.

Sourceval to_interface_list : 'a list t -> 'a t list

Create a list of interfaces from a single interface where each field is a list. Raises if all lists don't have the same length.

Sourcemodule All (M : Base.Monad.S) : sig ... end

Similar to Monad.all for lists -- combine and lift the monads to outside the interface.

Sourceval or_error_all : 'a Core.Or_error.t t -> 'a t Core.Or_error.t

Equivalent to All(Or_error).all. This is made a special case for convenience.

Sourcemodule type Comb = sig ... end
Sourcemodule Make_comb (Comb : Comb.S) : Comb with type comb = Comb.t
Sourcemodule Of_bits : Comb with type comb = Bits.t
Sourcemodule Of_signal : sig ... end
Sourcemodule Of_clocked_signal : sig ... end
Sourcemodule Of_always : sig ... end

Helper functions to ease usage of the Always API when working with interfaces.

Sourcemodule Names_and_widths : sig ... end
Sourceval wave_formats : Wave_format.t t

Optional Metadata

Sourceval to_untyped : 'a t -> 'a Hardcaml_kernel__.Clocking_intf.Untyped.t
Sourceval of_untyped : 'a Hardcaml_kernel__.Clocking_intf.Untyped.t -> 'a t
Sourceval add_clear : Hardcaml_kernel__.Signal__type.t t -> Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t t
Sourceval to_spec : Hardcaml_kernel__.Signal__type.t t -> Hardcaml_kernel__.Signal.Reg_spec.t
Sourceval to_spec_no_clear : Hardcaml_kernel__.Signal__type.t t -> Hardcaml_kernel__.Signal.Reg_spec.t
Sourceval clock : Hardcaml_kernel__.Signal__type.t t -> Hardcaml_kernel__.Signal__type.t
Sourceval reg : Hardcaml_kernel__.Signal__type.t t -> ?enable:Hardcaml_kernel__.Signal__type.t -> ?clear:Hardcaml_kernel__.Signal__type.t -> ?clear_to:Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t
Sourceval cut_through_reg : Hardcaml_kernel__.Signal__type.t t -> ?clear:Hardcaml_kernel__.Signal__type.t -> ?clear_to:Hardcaml_kernel__.Signal__type.t -> enable:Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t
Sourceval reg_no_clear : Hardcaml_kernel__.Signal__type.t t -> ?enable:Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t
Sourceval pipeline : ?attributes:Rtl_attribute.t list -> ?enable:Hardcaml_kernel__.Signal__type.t -> ?clear:Hardcaml_kernel__.Signal__type.t -> ?clear_to:Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t t -> n:int -> Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t
Sourceval pipeline_no_clear : ?attributes:Rtl_attribute.t list -> ?enable:Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t t -> n:int -> Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t
Sourceval reg_fb : ?enable:Hardcaml_kernel__.Signal__type.t -> ?clear:Hardcaml_kernel__.Signal__type.t -> ?clear_to:Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t t -> width:int -> f:(Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t) -> Hardcaml_kernel__.Signal__type.t
Sourceval reg_fb_and_next : ?enable:Hardcaml_kernel__.Signal__type.t -> ?clear:Hardcaml_kernel__.Signal__type.t -> ?clear_to:Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t t -> width:int -> f:(Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t) -> Hardcaml_kernel__.Signal__type.t * Hardcaml_kernel__.Signal__type.t
Sourceval reg_fb_and_next_no_clear : ?enable:Hardcaml_kernel__.Signal__type.t -> ?clear:Hardcaml_kernel__.Signal__type.t -> ?clear_to:Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t t -> width:int -> f:(Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t) -> Hardcaml_kernel__.Signal__type.t * Hardcaml_kernel__.Signal__type.t
Sourceval reg_fb_no_clear : ?enable:Hardcaml_kernel__.Signal__type.t -> ?clear:Hardcaml_kernel__.Signal__type.t -> ?clear_to:Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t t -> width:int -> f:(Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t) -> Hardcaml_kernel__.Signal__type.t
Sourcemodule Var : sig ... end
Sourcemodule Cdc : sig ... end

Utility functions for clock domain crossings.

Sourcemodule Clocked : sig ... end