Module Clocking.CdcSource

Utility functions for clock domain crossings.

Sourceval stretch : Hardcaml_kernel__.Signal__type.t t -> n:int -> Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t

Take a single cycle input pulse, and stretch it for n cycles. The output goes high on the same cycle as the input.

Sourceval stretch_no_clear : Hardcaml_kernel__.Signal__type.t t -> n:int -> Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t
Sourceval with_valid_pulse_detect_rising_edge : Hardcaml_kernel__.Signal__type.t t -> Hardcaml_kernel__.Signal__type.t With_valid.t -> Hardcaml_kernel__.Signal__type.t With_valid.t

Take a Signal.t With_valid.t that is in a slower clock and convert the valid pulse to a pulse in the faster clock.

Sourceval reg_no_clear_with_async_reg_annotation : num_additional_pipeline_stages:int -> Hardcaml_kernel__.Signal__type.t t -> Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t

Create 1 + num_additional_pipeline_stages registers in a pipeline with async_reg attribute set. Note this does not add any false path or timing constraints, the user needs to do that separately.