Hardcaml_kernel.SignalSourceHardware design datatype suitable for simulation and netlist generation
include S with type t := Hardcaml_kernel__.Signal__type.tInformation tracked by the signal.
val set_info :
Hardcaml_kernel__.Signal__type.t ->
info:info ->
Hardcaml_kernel__.Signal__type.tSet the information attached to a signal.
One or more string names applied to a signal. These will be used during RTL code generation and simulation to aid design inspection.
Returns the list of names and locations assigned to the signal.
Returns the list of names assigned to the signal.
Set the given names on the signal. Wipes any names currently set.
Reset any names for global signals.
Attributes are attached to signals and written during RTL generation. They can be used to control downstream synthesis and place and route tools. They do not otherwise affect the Hardcaml circuit.
val add_attribute :
Hardcaml_kernel__.Signal__type.t ->
Rtl_attribute.t ->
Hardcaml_kernel__.Signal__type.tAdd an attribute to node.
Returns attributes associated to the signal.
Set the format used to display the signal
val (--$) :
Hardcaml_kernel__.Signal__type.t ->
Wave_format.t ->
Hardcaml_kernel__.Signal__type.tA comment can be associated with a signal, and this is sometimes useful to pass information to downstream tooling (specifically Verilator).
val set_comment :
Hardcaml_kernel__.Signal__type.t ->
string ->
Hardcaml_kernel__.Signal__type.tSet the comment associated with the signal. This is currently only supported in Verilog.
Remove the comment associated with the signal. This is currently only supported in Verilog.
Returns comment associated with the signal.
val add_mux_waiver_exn :
Hardcaml_kernel__.Signal__type.t ->
int Coverage_prim.Waiver.t ->
Hardcaml_kernel__.Signal__type.tAttach a waiver for mux coverage. Raises if the signal is not a mux.
val add_cases_waiver_exn :
Hardcaml_kernel__.Signal__type.t ->
Coverage_prim.Case.t Coverage_prim.Waiver.t ->
Hardcaml_kernel__.Signal__type.tAttach a waiver for cases coverage. Raises if the signal is not a cases signal.
val add_register_waiver_exn :
Hardcaml_kernel__.Signal__type.t ->
Coverage_prim.Toggle.t Coverage_prim.Waiver.t ->
Hardcaml_kernel__.Signal__type.tAttach a waiver for register coverage. Raises if the signal is not a register or it is an always state register.
val add_always_state_waiver_exn :
Hardcaml_kernel__.Signal__type.t ->
string Coverage_prim.Waiver.t ->
Hardcaml_kernel__.Signal__type.tAttach a state waiver to an always state register. Raises if the signal is not an always state register.
val add_always_state_transition_waiver_exn :
Hardcaml_kernel__.Signal__type.t ->
string Coverage_prim.Transition.t Coverage_prim.Waiver.t ->
Hardcaml_kernel__.Signal__type.tAttach as transition wavier to an always state register. Raises if the signal is not an always state register.
Specification of the module level input and output ports. Ports are represented in Hardcaml as wires with a single name. Note that Hardcaml will generally rewrite and legalize names depending on context but will not do so for ports.
Creates an input.
Creates an output.
Wires are used in Hardcaml to conenct two signals together. They are first created then assigned to (internally they have a mutable reference to their driver). Wires are how we can create cycles which we require in order to build logic like, for example, a counter.
It is entirely possible to create combinational loops using wires. Often this is not the intent and Hardcaml has functions to detect this - for example, Cyclesim will fail if there is such a loop.
Creates an unassigned wire.
Creates an assigned wire.
Assigns to wire.
The main combinational logic API for creating things like adders, multiplexers etc. This API is the same as provided by Bits.t.
By default Hardcaml performs constant propogation over signals - operations with purely constant values (and some other simple cases such as a &: vdd) will be simplified. You can avoid this by using the operations from the Unoptimized module.
Combinational logic API with constant propogation optimizations.
include Comb.S with type t := Hardcaml_kernel__.Signal__type.tinclude Base.Equal.S__local with type t := Hardcaml_kernel__.Signal__type.tlogic 1
logic 0
create signal from a constant
convert binary string to constant
Convert integer to constant. Negative values are sign extended up to width. Input values which are larger or smaller than those representable in width bits are truncated.
Same as of_int_trunc
Convert non-negative values to constant. Input values which are not representable in width bits will raise.
Convert signed values to constant. Input values which are not representable in width bits will raise.
val of_hex :
?signedness:Signedness.t ->
width:int ->
string ->
Hardcaml_kernel__.Signal__type.tconvert hex string to a constant. If the target width is greater than the hex length and signedness is Signed then the result is sign extended. Otherwise the result is zero padded.
val of_octal :
?signedness:Signedness.t ->
width:int ->
string ->
Hardcaml_kernel__.Signal__type.tconvert octal string to a constant. If the target width is greater than the octal length and signedness is Signed then the result is sign extended. Otherwise the result is zero padded.
Convert an arbitrarily wide integer value to a constant.
convert verilog style or binary string to constant
convert IntbitsList to constant
convert a char to an 8 bit constant
convert a bool to vdd or gnd
convert a string to a series of 8-bit characters and concatenate them into a signal, with the first character of the string being in the least-significant bits
convert a string to a series of 8-bit characters and concatenate them into a signal, with the first character of the string being in the most-significant bits
create random constant vector of given width
zero w makes a the zero valued constant of width w
ones w makes a constant of all ones of width w
one w makes a one valued constant of width w
the empty signal
returns true if the signal is empty
val (--) :
loc:lexing_position ->
Hardcaml_kernel__.Signal__type.t ->
string ->
Hardcaml_kernel__.Signal__type.tnames a signal
let a = a -- "a" in ...
signals may have multiple names.
returns the width (number of bits) of a signal.
let w = width s in ...
addess_bits_for num_elements returns the address width required to index num_elements.
It is the same as Int.ceil_log2, except it wll return a minimum value of 1 (since you cannot have 0 width vectors). Raises if num_elements is < 0.
num_bits_to_represent x returns the number of bits required to represent the number x, which should be >= 0.
convert the signal to a constant
concat_msb ts concatenates a list of signals - the msb of the head of the list will become the msb of the result.
let c = concat_msb [ a; b; c ] in ...
concat_msb raises if ts is empty or if any t in ts is empty.
Similar to concat_msb except the lsb of the head of the list will become the lsb of the result.
val split_lsb :
?exact:bool ->
part_width:int ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t listSplit signal into a list of signals with width equal to part_width. The least significant bits are at the head of the returned list. If exact is true the input signal width must be exactly divisable by part_width. When exact is false and the input signal width is not exactly divisible by part_width, the last element will contains residual bits.
eg:
split_lsb ~part_width:4 16b0001_0010_0011_0100 =
[ 4b0100; 4b0011; 4b0010; 4b0001 ]
split_lsb ~exact:false ~part_width:4 17b11_0001_0010_0011_0100 =
[ 4b0100; 4b0011; 4b0010; 4b0001; 2b11 ]val split_msb :
?exact:bool ->
part_width:int ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t listLike split_lsb except the most significant bits are at the head of the returned list. Residual bits when exact is false goes to the last element of the list, so in the general case split_lsb is not necessarily equivalent to split_msb |> List.rev.
val mux :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t list ->
Hardcaml_kernel__.Signal__type.tmultiplexer.
let m = mux sel inputs in ...
Given l = List.length inputs and w = width sel the following conditions must hold:
l <= Int.pow 2 w, l >= 1
If l < Int.pow 2 w, the last input is repeated.
All inputs provided must have the same width, which will in turn be equal to the width of m.
val mux_strict :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t list ->
Hardcaml_kernel__.Signal__type.tSame as mux except requires:
l = Int.pow 2 w
val (@:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tconcatenate two signals.
let c = a @: b in ...
equivalent to concat [ a; b ]
val select :
Hardcaml_kernel__.Signal__type.t ->
high:int ->
low:int ->
Hardcaml_kernel__.Signal__type.tselect t ~high ~low selects from t bits in the range high...low, inclusive. select raises unless high and low fall within 0 .. width t - 1 and high >= lo.
select a single bit
get most significant bit
get least significant bits
get least significant bit
get most significant bits
val drop_bottom :
Hardcaml_kernel__.Signal__type.t ->
width:int ->
Hardcaml_kernel__.Signal__type.tdrop_bottom s ~width drop bottom width bits of s
val drop_top :
Hardcaml_kernel__.Signal__type.t ->
width:int ->
Hardcaml_kernel__.Signal__type.tdrop_top s ~width drop top width bits of s
val sel_bottom :
Hardcaml_kernel__.Signal__type.t ->
width:int ->
Hardcaml_kernel__.Signal__type.tsel_bottom s ~width select bottom width bits of s
val sel_top :
Hardcaml_kernel__.Signal__type.t ->
width:int ->
Hardcaml_kernel__.Signal__type.tsel_top s ~width select top width bits of s
val (.:[]) :
Hardcaml_kernel__.Signal__type.t ->
(int * int) ->
Hardcaml_kernel__.Signal__type.tx.:[hi, lo] == select x hi lo
val (.:+[]) :
Hardcaml_kernel__.Signal__type.t ->
(int * int option) ->
Hardcaml_kernel__.Signal__type.tx.:+[lo, width] == select x (lo + width - 1) lo. If width is None it selects all remaining msbs of the vector ie x.:+[lo,None] == drop_bottom x lo
val (.:-[]) :
Hardcaml_kernel__.Signal__type.t ->
(int option * int) ->
Hardcaml_kernel__.Signal__type.tx.:-[hi, width] == select x hi (hi - width + 1). If hi is None it defaults to the msb of the vector ie x.:-[None, width] == sel_top x width
x.(i) == bit x i
val insert :
into:Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
at_offset:int ->
Hardcaml_kernel__.Signal__type.tinsert ~into:t x ~at_offset insert x into t at given offet
val mux2 :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tmux2 c t f 2 input multiplexer. Selects t if c is high otherwise f.
t and f must have same width and c must be 1 bit.
Equivalent to mux c [f; t]
val mux_init :
Hardcaml_kernel__.Signal__type.t ->
int ->
f:(int -> Hardcaml_kernel__.Signal__type.t) ->
Hardcaml_kernel__.Signal__type.tval cases :
default:Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
(Hardcaml_kernel__.Signal__type.t * Hardcaml_kernel__.Signal__type.t) list ->
Hardcaml_kernel__.Signal__type.tcases ~default select [(match0, value0); (match0, value0)...] compares select with matchN and outputs valueN. If nothing matches default is output. This construct maps to a case statement.
The matchN values must be constants.
val (&:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tlogical and
val (&&:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.ta <>:. 0 &: b <>:. 0
val (|:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tlogical or
val (||:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.ta <>:. 0 |: b <>:. 0
val (^:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tlogic xor
logical not
val (+:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.taddition
val (-:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tsubtraction
negation
val (*:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tunsigned multiplication
val (*+) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tsigned multiplication
val (==:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tequality
val (<>:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tinequality
val (<:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tless than
val lt :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tval (>:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tgreater than
val (<=:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tless than or equal to
val (>=:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tgreater than or equal to
val (<+) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tsigned less than
val (>+) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tsigned greater than
val (<=+) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tsigned less than or equal to
val (>=+) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tsigned greated than or equal to
val (-->:) :
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tPropositional logic implication operator
create string from signal
to_int t treats t as unsigned and resizes it to fit exactly within an OCaml Int.t.
width t > Int.num_bits then the upper bits are truncated.width t >= Int.num_bits and bit t (Int.num_bits-1) = vdd (i.e. the msb of the resulting Int.t is set), then the result is negative.t is Signal.t and not a constant value, an exception is raised.Same as to_int_trunc.
to_signed_int t treats t as signed and resizes it to fit exactly within an OCaml Int.t.
t is Signal.t and not a constant value, an exception is raised.to_unsigned_int t treats t as unsigned and resizes it to fit exactly within an OCaml Int.t.
int value must be unsigned (so the max width is Int.num_bits - 1).t is Signal.t and not a constant value, an exception is raised.Convert signal to a bool. The signal must be 1 bit wide.
Convert signal to a char. The signal must be 8 bits wide.
Convert into a string, with the first character being from the least-significant bits of the signal. The signal width must be a multiple of 8 bits.
Convert into a string, with the first character being from the most-significant bits of the signal. The signal width must be a multiple of 8 bits.
create binary string from signal
Convert bits to a Zarith.t
convert signal to a list of bits with msb at head of list
convert signal to a list of bits with lsb at head of list
val repeat :
Hardcaml_kernel__.Signal__type.t ->
count:int ->
Hardcaml_kernel__.Signal__type.trepeat signal count times
val split_in_half_msb :
?msbs:int ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t * Hardcaml_kernel__.Signal__type.tSplit signal in half. The most significant bits will be in the left half of the returned tuple.
msbs is not provided, the signal will be split in half with the MSB part possibly containing one more bit.msbs is provided, msbs most significant bits will be split off.val split_in_half_lsb :
?lsbs:int ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t * Hardcaml_kernel__.Signal__type.tSame as split_in_half_msb, but
lsbs is not provided, the LSB part might have one more bit.lsbs is provided, lsbs least significant bits will be split off.The most significant bits will still be in the left half of the tuple.
shift left logical
shift right logical
shift right arithmetic
rotate left
rotate right
val log_shift :
f:
(Hardcaml_kernel__.Signal__type.t ->
by:int ->
Hardcaml_kernel__.Signal__type.t) ->
Hardcaml_kernel__.Signal__type.t ->
by:Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tshift by variable amount
val uresize :
Hardcaml_kernel__.Signal__type.t ->
width:int ->
Hardcaml_kernel__.Signal__type.turesize t ~width:w returns the unsigned resize of t to width w. If w = width t, this is a no-op. If w < width t, this selects the w low bits of t. If w > width t, this extends t with zero (w - width t).
val sresize :
Hardcaml_kernel__.Signal__type.t ->
width:int ->
Hardcaml_kernel__.Signal__type.tsresize t ~width:w returns the signed resize of t to width w. If w = width t, this is a no-op. If w < width t, this selects the w low bits of t. If w > width t, this extends t with w - width t copies of msb t.
val uextend :
Hardcaml_kernel__.Signal__type.t ->
width:int ->
Hardcaml_kernel__.Signal__type.tuextend t ~width:w behaves similarly to uresize t ~width:w but asserts that w >= width to prevent inadvertently chopping the signal.
val sextend :
Hardcaml_kernel__.Signal__type.t ->
width:int ->
Hardcaml_kernel__.Signal__type.tsextend t ~width:w behaves similarly to sresize t ~width:w but asserts that w >= width to prevent inadvertently chopping the signal.
unsigned resize by +1 bit
signed resize by +1 bit
val resize_list :
resize:
(Hardcaml_kernel__.Signal__type.t ->
int ->
Hardcaml_kernel__.Signal__type.t) ->
Hardcaml_kernel__.Signal__type.t list ->
Hardcaml_kernel__.Signal__type.t listresize_list ~resize l finds the maximum width in l and applies resize el max to each element.
val resize_op2 :
resize:
(Hardcaml_kernel__.Signal__type.t ->
int ->
Hardcaml_kernel__.Signal__type.t) ->
(Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t) ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tresize_op2 ~resize f a b applies resize x w to a and b where w is the maximum of their widths. It then returns f a b
fold 'op' though list
reverse bits
val mod_counter :
max:int ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tmod_counter max t is if t = max then 0 else (t + 1), and can be used to count from 0 to max then from zero again. If max == (1<<n - 1), then a comparator is not generated and overflow arithmetic is used instead.
compute_arity ~steps num_values computes the tree arity required to reduce num_values in steps. steps<=0 raises.
compute_tree_branches ~steps num_values returns a list of length steps of branching factors required to reduce num_values. This tends to produce a slightly more balanced sequence than just applying compute_arity at every step.
tree ~arity ~f input creates a tree of operations. The arity of the operator is configurable. tree raises if input = [].
val priority_select :
?branching_factor:int ->
(Hardcaml_kernel__.Signal__type.t, Hardcaml_kernel__.Signal__type.t)
Hardcaml_kernel__.Comb_intf.with_valid2
list ->
(Hardcaml_kernel__.Signal__type.t, Hardcaml_kernel__.Signal__type.t)
Hardcaml_kernel__.Comb_intf.with_valid2priority_select cases returns the value associated with the first case whose valid signal is high. valid will be set low in the returned with_valid if no case is selected.
val priority_select_with_default :
?branching_factor:int ->
(Hardcaml_kernel__.Signal__type.t, Hardcaml_kernel__.Signal__type.t)
Hardcaml_kernel__.Comb_intf.with_valid2
list ->
default:Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tSame as priority_select except returns default if no case matches.
val onehot_select :
?branching_factor:int ->
(Hardcaml_kernel__.Signal__type.t, Hardcaml_kernel__.Signal__type.t)
Hardcaml_kernel__.Comb_intf.with_valid2
list ->
Hardcaml_kernel__.Signal__type.tSelect a case where one and only one valid signal is enabled. If more than one case is valid then the return value is undefined. If no cases are valid, 0 is returned by the current implementation, though this should not be relied upon.
val popcount :
?branching_factor:int ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tpopcount t returns the number of bits set in t.
val binary_to_byte_qualifier :
num_bytes:int ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tbinary_to_byte_qualifier ~num_bytes t returns a byte qualifier encoding of a binary size for use when encoding contiguous byte enables or byte keep signals.
val is_pow2 :
?branching_factor:int ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tis_pow2 t returns a bit to indicate if t is a power of 2.
val leading_ones :
?branching_factor:int ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tleading_ones t returns the number of consecutive 1s from the most significant bit of t down.
val trailing_ones :
?branching_factor:int ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.ttrailing_ones t returns the number of consecutive 1s from the least significant bit of t up.
val leading_zeros :
?branching_factor:int ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tleading_zeros t returns the number of consecutive 0s from the most significant bit of t down.
val trailing_zeros :
?branching_factor:int ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.ttrailing_zeros t returns the number of consecutive 0s from the least significant bit of t up.
val floor_log2 :
?branching_factor:int ->
Hardcaml_kernel__.Signal__type.t ->
(Hardcaml_kernel__.Signal__type.t, Hardcaml_kernel__.Signal__type.t)
Hardcaml_kernel__.Comb_intf.with_valid2floor_log2 x returns the floor of log-base-2 of x. x is treated as unsigned and an error is indicated by valid = gnd in the return value if x = 0.
val ceil_log2 :
?branching_factor:int ->
Hardcaml_kernel__.Signal__type.t ->
(Hardcaml_kernel__.Signal__type.t, Hardcaml_kernel__.Signal__type.t)
Hardcaml_kernel__.Comb_intf.with_valid2ceil_log2 x returns the ceiling of log-base-2 of x. x is treated as unsigned and an error is indicated by valid = gnd in the return value if x = 0.
convert binary to onehot
convert onehot to binary
convert binary to gray code
convert gray code to binary
val gray_increment :
Hardcaml_kernel__.Signal__type.t ->
by:int ->
Hardcaml_kernel__.Signal__type.tIncrement a gray code value. The implementation converts to binary, increments the binary value, then converts back to gray code.
any_bit_set t returns vdd if at least one bit if set in t and gnd otherwise.
all_bits_set t returns vdd if all bits in t are set and gnd otherwise.
no_bits_set t returns vdd if no bits in t are set and gnd otherwise.
Increment (defaults to 1). Wrap on overflow.
Decrement (defaults to 1). Wrap on overflow.
Concatention, selection and resizing functions for signals encoded as an option where None means zero width.
Unsigned vector operations (ie may operate on Bits.t or Signal.t directly).
Signed vector operations (ie may operate on Bits.t or Signal.t directly).
Combinational logic API without constant propogation optimizations.
Convert the signal to bits. Raises if the signal is not a constant.
Registers are configured using a Reg_spec.t. This encodes the clock, synchronous clear, and asychronous reset used.
type 'a with_register_spec =
?enable:Hardcaml_kernel__.Signal__type.t ->
?initialize_to:Bits.t ->
?reset_to:Bits.t ->
?clear:Hardcaml_kernel__.Signal__type.t ->
?clear_to:Hardcaml_kernel__.Signal__type.t ->
Reg_spec.t ->
'aval reg :
(Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t)
with_register_specval reg_fb :
(width:int ->
f:(Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t) ->
Hardcaml_kernel__.Signal__type.t)
with_register_specval reg_fb_and_next :
(width:int ->
f:(Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal__type.t) ->
Hardcaml_kernel__.Signal__type.t * Hardcaml_kernel__.Signal__type.t)
with_register_specLike reg_fb but returns both the registered value and the next cycle's value (i.e. the output of f prev_value). The next value ignores clear or reset if applied, i.e. if clear is applied, next will still be f prev_value rather than clear_to.
val pipeline :
?attributes:Rtl_attribute.t list ->
(n:int ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t)
with_register_specPipeline a signal n times with the given register specification. If set, a list of RTL attributes will also be applied to each register created.
val cut_through_reg :
?initialize_to:Bits.t ->
?reset_to:Bits.t ->
?clear:Hardcaml_kernel__.Signal__type.t ->
?clear_to:Hardcaml_kernel__.Signal__type.t ->
Reg_spec.t ->
enable:Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tA register which forwards its input value to the output during cycles in which it is enabled.
Implemented as a register with a mux on the output. Note that the cut through bevahiour will also occur if enable is high during a clear (or even reset) operation.
val prev :
(Hardcaml_kernel__.Signal__type.t ->
(int -> Hardcaml_kernel__.Signal__type.t) Base.Staged.t)
with_register_specStaged.unstage (prev spec ?enable d) returns a function prev n which provides d registered n times (ie the value of d n cycles in the past). n=0 means the current (combinational value).
The internal registers are shared between calls. When called multiple times with a maximum value of n exactly n registers are created.
val counter :
?enable:Hardcaml_kernel__.Signal__type.t ->
?initialize_to:Bits.t ->
?reset_to:Bits.t ->
?clear:Hardcaml_kernel__.Signal__type.t ->
?clear_to:Hardcaml_kernel__.Signal__type.t ->
?by:int ->
Reg_spec.t ->
width:int ->
Hardcaml_kernel__.Signal__type.tBasic counter. Adds by on each enabled cycle. Wraps on over/underflow.
multiport_memory provides the low-level primitive from which Hardcaml memories are created. It provides a memory with an arbitrary number of read and write ports that is asychronously read.
By default synthesizers will infer either LUT ram or register banks from this primitive.
Limiting the number of read/write ports and placing a register on the read address or read output port will allow synthesizers to infer single or simple dual port RAM from RTL. ram_rbw and ram_wbr are examples of this.
val multiport_memory :
?enable_modelling_features:bool ->
?verbose:bool ->
?name:string ->
?attributes:Rtl_attribute.t list ->
?initialize_to:Bits.t array ->
int ->
write_ports:Hardcaml_kernel__.Signal__type.t Write_port.t array ->
read_addresses:Hardcaml_kernel__.Signal__type.t array ->
Hardcaml_kernel__.Signal__type.t arraySynchronous write / asynchronous read memory. Supports an arbitrary number of read_addresses and write_ports. Placement of registers on the address or data output will allow synthesizers to infer RAMs from generated RTL (see also Ram.create which builds on this primitive to implement inferred memories).
Any provided attributes are applied to the memory array itself.
The memory may be initialized by providing initialize_to.
enable_modelling_features allows multibit enable and port scaling features. In both cases they will generate valid synthesizable RTL but backend tool inference is unlikely to work leading to sub-optimal designs.
In both cases extra read/write ports are generated and the internal RAM may be narrowed to support the feature.
For multibit enables the number of write enables must evenly divide the write data width or an exception will be raised.
For port scaling the read/write port ratio must be a power of two. It is specified by making the read and write address widths different and scaling the write data width appropriately. The size and initialize_to parameters are specified relative to the write port with the widest data bus.
val rom :
read_addresses:Hardcaml_kernel__.Signal__type.t array ->
Bits.t array ->
Hardcaml_kernel__.Signal__type.t arrayA multi-read port asynchronous ROM built from a memory primitive. This can be used to map ROMs into RAM resources by registering the output.
val memory :
?attributes:Rtl_attribute.t list ->
int ->
write_port:Hardcaml_kernel__.Signal__type.t Write_port.t ->
read_address:Hardcaml_kernel__.Signal__type.t ->
Hardcaml_kernel__.Signal__type.tval ram_wbr :
?name:string ->
?attributes:Rtl_attribute.t list ->
write_port:Hardcaml_kernel__.Signal__type.t Write_port.t ->
read_port:Hardcaml_kernel__.Signal__type.t Read_port.t ->
int ->
Hardcaml_kernel__.Signal__type.tval ram_rbw :
?name:string ->
?attributes:Rtl_attribute.t list ->
write_port:Hardcaml_kernel__.Signal__type.t Write_port.t ->
read_port:Hardcaml_kernel__.Signal__type.t Read_port.t ->
int ->
Hardcaml_kernel__.Signal__type.tOperate on the underlying representation of the signal type. This is useful if you need to operate on the underlying Signal.Type that represents the Signal.S that you are working with or to reflect on the extra information attached to the specific Signal.S (like clock domains for Clocked.t).
Return the underlying representation for the signal.
Construct a signal from the underlying representation and the information tracked by this signal.
val update_rep :
Hardcaml_kernel__.Signal__type.t ->
info:info ->
Hardcaml_kernel__.Signal__type.tUpdate the information attached to this signal.
Pretty printer.
Returns the unique id of the signal.