Module Always.VariableSource

The type of variables in guarded assignments. Variables may be asychronous wires, or synchronous regs. The current value of the variable may be accessed through the value field below.

Sourcetype internal
Sourcetype t = private {
  1. value : Hardcaml_kernel__.Signal__type.t;
  2. internal : internal;
}
Sourceval sexp_of_t : t -> Sexplib0.Sexp.t
Sourceval value : t -> Hardcaml_kernel__.Signal__type.t

gets the current value of the variable

Sourceval wire : here:lexing_position -> default:Hardcaml_kernel__.Signal__type.t -> unit -> t

create a wire

Sourceval reg : here:lexing_position -> ?enable:Hardcaml_kernel__.Signal__type.t -> ?initialize_to:Bits.t -> ?reset_to:Bits.t -> ?clear:Hardcaml_kernel__.Signal__type.t -> ?clear_to:Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal.Reg_spec.t -> width:int -> t

create a register

Sourceval cut_through_reg : ?enable:Hardcaml_kernel__.Signal__type.t -> ?initialize_to:Bits.t -> ?reset_to:Bits.t -> ?clear:Hardcaml_kernel__.Signal__type.t -> ?clear_to:Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal.Reg_spec.t -> width:int -> t

creates a register which forwards its input value to the output during cycles in which it is enabled.

Sourceval pipeline : here:lexing_position -> ?enable:Hardcaml_kernel__.Signal__type.t -> ?initialize_to:Bits.t -> ?reset_to:Bits.t -> ?clear:Hardcaml_kernel__.Signal__type.t -> ?clear_to:Hardcaml_kernel__.Signal__type.t -> Hardcaml_kernel__.Signal.Reg_spec.t -> width:int -> depth:int -> t

create a pipeline of registers

Sourceval __ppx_auto_name : t -> string -> t
Sourcemodule Expert : sig ... end